ASML and Chip Manufacturing

Why This Matters

Every advanced GPU used for AI training and inference (NVIDIA H100, B200, AMD MI300X) is manufactured using ASML's extreme ultraviolet (EUV) lithography machines. There is no alternative supplier. This makes ASML one of the most consequential single points of failure in the AI supply chain.

Understanding chip manufacturing is not optional for anyone thinking seriously about AI compute scaling. The question "can we train a 10x larger model next year?" depends on semiconductor fabrication capacity as much as it depends on algorithms. Scaling laws predict the compute needed, but the hardware supply chain determines whether that compute is available.

Mental Model

A chip is made by projecting patterns of light onto a silicon wafer coated with photosensitive material (photoresist). The smallest features you can print are limited by the wavelength of light. Shorter wavelength means smaller transistors. Smaller transistors mean more compute per chip.

EUV lithography uses 13.5nm wavelength light, roughly 14x shorter than the 193nm wavelength of the previous generation (deep ultraviolet, DUV). This is what enables sub-7nm transistor nodes.

The Physics of EUV

Definition

Rayleigh Resolution Criterion

The minimum resolvable feature size $W$ in optical lithography is:

$W = k_1 \cdot \frac{\lambda}{NA}$

where $\lambda$ is the wavelength, $NA$ is the numerical aperture of the projection optics, and $k_1$ is a process-dependent factor (typically $0.25 \leq k_1 \leq 0.5$).

For EUV: $\lambda = 13.5\text{nm}$, $NA \approx 0.33$ (current systems) or $0.55$ (High-NA, shipping 2025+). This gives minimum features around $8\text{nm}$ for current systems and potentially $5\text{nm}$ for High-NA.

Proposition

Lithography Resolution Scaling

Statement

At fixed $k_1$ and $NA$, the minimum feature size scales linearly with wavelength. The transition from DUV ($\lambda = 193\text{nm}$) to EUV ($\lambda = 13.5\text{nm}$) reduced the resolution limit by a factor of approximately 14, enabling the jump from multi-patterning at 7nm to single-patterning at comparable feature sizes.

Intuition

DUV lithography at 193nm hit a wall around 2015. To print features below about 40nm, fabs had to expose each layer multiple times with different masks (multi-patterning). This is slow, expensive, and introduces alignment errors. EUV eliminates the need for multi-patterning at current nodes, simplifying manufacturing and improving yield.

Failure Mode

The Rayleigh criterion is a first-order approximation. Real lithography involves stochastic effects (photon shot noise, resist chemistry randomness, subject to floating-point arithmetic limits in simulation) that become dominant at very small feature sizes. At sub-3nm nodes, even EUV will require multi-patterning or a transition to High-NA EUV.

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How EUV Light Is Generated

EUV light cannot be generated by conventional lasers or lamps. The process:

1. A high-power CO2 laser fires at tin droplets (50,000 droplets per second, each about 25 micrometers in diameter).
2. Each droplet is hit twice: a pre-pulse flattens it into a pancake shape, then the main pulse vaporizes it into a plasma at approximately 500,000 degrees.
3. The tin plasma emits EUV radiation at 13.5nm.
4. Multilayer mirrors (alternating layers of molybdenum and silicon, each a few nanometers thick) collect and focus the EUV light. Each mirror reflects only about 70% of incident EUV, so a system with 10+ mirrors loses most of the light.
5. The collected EUV light projects a pattern from the reticle (mask) onto the wafer.

The conversion efficiency from laser power to in-band EUV at the plasma source is roughly 5-6%. A modern EUV system uses a 40kW CO2 laser to produce several kW of in-band 13.5nm radiation at the tin plasma. Only a small fraction (roughly 2-5%) survives the collector mirror, the illuminator, the reticle, and the projection optics. The commonly quoted figure of approximately 250W refers to EUV power at the wafer plane, which is what actually exposes photoresist. Throughput (wafers per hour) scales with this wafer-plane power, not the plasma-source power.

ASML's Position

ASML holds a monopoly on EUV lithography systems for several reasons:

Technology integration: An EUV scanner contains over 100,000 components from hundreds of suppliers. ASML is the integrator. Key subsystems come from Zeiss (optics), Trumpf (laser source), and ASML itself (stage and control systems). No other company has replicated this integration.

Development cost: ASML spent over 20 years and billions of euros developing EUV, with funding from Intel, Samsung, and TSMC. The technology was repeatedly declared impossible before it worked.

Installed base: Each EUV system costs roughly 200 million to 400 million USD, and High-NA systems (EXE:5000, EXE:5200) exceed 350 million USD each. TSMC, Samsung, and Intel are the primary customers. As of early 2026, ASML has shipped roughly 250 to 280 EUV systems (0.33 NA Twinscan NXE) worldwide, plus five or more High-NA (0.55 NA) systems delivered to Intel, TSMC, Samsung, imec, and SK hynix for pilot ramp.

Supply Chain Concentration

The semiconductor supply chain has multiple single points of failure:

A disruption at any of these points constrains AI chip supply. The geographic concentration (Netherlands, Germany, Taiwan, South Korea) adds geopolitical risk.

High-Bandwidth Memory and CoWoS Advanced Packaging

Modern AI accelerators (NVIDIA H100, H200, B200, AMD MI300X, Google TPU v5, Meta MTIA) are bottlenecked as often by memory bandwidth and packaging capacity as by logic compute. Two chokepoints dominate.

High-Bandwidth Memory (HBM). HBM is a stack of DRAM dies connected by through-silicon vias (TSVs) and mounted next to the compute die on a silicon interposer. HBM3E is the current production generation (up to 1.2 TB/s per stack, 36 GB per stack at 12-Hi); HBM4 is sampling in 2025-2026 with higher per-pin rates and wider buses. Supply is concentrated in SK hynix, Samsung, and Micron, with SK hynix currently leading in HBM3E shipments to NVIDIA. HBM yield is limited by TSV alignment and known-good-die stacking, and capacity has been the binding constraint on H100 and B200 throughput through 2024-2026.

CoWoS (Chip-on-Wafer-on-Substrate). TSMC's advanced packaging technology co-integrates a logic die with HBM stacks on a silicon interposer. CoWoS-S uses a monolithic silicon interposer suitable for one logic die plus up to eight HBM stacks (H100-class). CoWoS-L uses a larger multi-die interposer with local silicon bridges for the B200 and GB200, supporting two reticle-stitched logic dies and higher HBM counts. CoWoS capacity has been the single most cited capacity constraint on AI accelerator output in public TSMC and NVIDIA earnings calls during 2024-2026, and TSMC has been doubling CoWoS capacity roughly annually. See the GPU compute model and scaling compute-optimal training for how these hardware constraints shape practical training throughput.

Export Controls and Geopolitics

Semiconductor manufacturing equipment is subject to active export control regimes. The US Bureau of Industry and Security (BIS) published the October 7, 2022 rules restricting export of advanced logic (sub-14nm/16nm) and leading HBM fabrication tools to Chinese end users, followed by further tightening in October 2023 and subsequent updates. The Netherlands aligned via Dutch export licensing: ASML EUV (all NXE and EXE systems) cannot be shipped to Chinese fabs, and since 2024 certain DUV immersion tools (NXT:2000i and above) also require licenses that have been denied for advanced-node Chinese customers.

The practical effect is a bifurcated leading-edge fab ecosystem. Chinese foundries (SMIC, CXMT) are capped at DUV-based nodes and multi-patterning, while TSMC, Samsung, and Intel retain EUV access. This bifurcation propagates up the stack: domestic Chinese AI accelerators (Huawei Ascend, Biren) must use older process nodes or export-compliant HBM, limiting their compute density relative to the leading edge.

Single-source chokepoints. ASML is the only supplier of EUV lithography worldwide. TSMC is the only foundry currently shipping leading-edge logic below N3 at volume. Taken together, ASML plus TSMC plus SK hynix HBM form a narrow pipeline through which nearly all frontier AI compute must pass. This concentration is the dominant geopolitical risk factor in AI supply chain analysis.

Relevance to AI Compute

The connection from lithography to AI models:

1. Transistor density determines compute per chip. The H100 has 80 billion transistors on TSMC 4nm (which uses EUV). The B200 has approximately 208 billion transistors on TSMC 4NP.
2. EUV throughput limits chip supply. Each EUV system processes roughly 100-150 wafers per hour. A single wafer yields a limited number of large AI chips (the H100 die is about 814mm^2).
3. High-NA EUV enables future scaling. The next generation of AI chips (2nm and below) will require High-NA EUV, of which ASML has delivered only a handful of systems to date.
4. Capital expenditure is enormous. A leading-edge fab costs more than 20 billion USD to build and equip. The EUV systems alone account for a significant fraction of this cost.

Common Confusions

Watch Out

Node names do not correspond to physical dimensions

TSMC 3nm does not mean transistors with 3nm features. Node names are marketing labels. Actual minimum metal pitch on TSMC N3 is approximately 23nm. The relationship between node names and physical dimensions diverged around 2010.

Watch Out

ASML does not fabricate chips

ASML makes the lithography machines. TSMC, Samsung, and Intel use those machines to fabricate chips. ASML is an equipment vendor, not a foundry. The distinction matters: ASML's bottleneck is machine production capacity, while TSMC's bottleneck is fab utilization and yield.

Watch Out

More EUV machines does not linearly increase chip output

Chip manufacturing involves 60-80 lithography steps, of which only a fraction use EUV (the rest use DUV). Other steps (deposition, etching, inspection, packaging) also constrain throughput. Adding EUV capacity helps only if it is the binding constraint.

Exercises

ExerciseCore

Problem

An EUV system with $\lambda = 13.5\text{nm}$ and $NA = 0.33$ uses $k_1 = 0.3$. What is the minimum resolvable feature size? How does this change with High-NA ($NA = 0.55$)?

Hint

Reveal Solution

ExerciseAdvanced

Problem

If each EUV mirror reflects 70% of incident light and the optical system has 11 mirrors between the plasma source and the wafer, what fraction of in-band EUV power at the plasma source reaches the wafer? If the wafer-plane power is approximately 250W, what must the in-band EUV power at the plasma source be to deliver it?

Hint

Reveal Solution

References

Canonical:

• Mack, Fundamental Principles of Optical Lithography (2007), Chapters 1-3

Current:

• ASML Annual Reports and Technology Updates (2024-2025), including High-NA EUV shipment disclosures
• Jiang & Wong, "EUV Lithography for Advanced Semiconductor Manufacturing" (Nature Reviews Electrical Engineering, 2024)
• US Bureau of Industry and Security, "Implementation of Additional Export Controls: Certain Advanced Computing and Semiconductor Manufacturing Items" (Federal Register, October 7, 2022), and October 2023 updates
• TSMC quarterly earnings transcripts (2024-2026) on CoWoS capacity ramp
• SK hynix and Samsung investor disclosures on HBM3E and HBM4 roadmaps (2024-2026)